Pay Rate: 85/hr to 95/hr on W2
Remote
• Ideally Masters + 5 years or Bachelors + 8 years is preferred
• Proficient in IP level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM testbenches and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, C, and C++
• Developing UVM based verification frameworks and testbenches, processes and flows
• Automating workflows in a distributed compute environment.
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
4 days ago Be among the first 25 applicantsProfessional Dog Sitter - A Purrfectly Flexible Opportunity!Do you love dogs? Are you great... ...private walks or 60 minute group walks). Before your first sitting visit, youll meet each client and their dog in person for a meet...
...Job Description Job Description Farm Bill Wildlife Biologist I/II Locations: Austin, Dodge Center, or Albert Lea, Minnesota... ...capacity with Pheasants Forever, Inc. (PF), USDA Natural Resources Conservation Service (NRCS), Soil and Water Conservation Districts (SWCDs),...
DFINITY is looking for a Senior UI/UX designer to join distinguished team that's building an AI-driven no-code application development platform for ICP. One of the first problems youll solve is designing the project lifecycle user experience.This is a hybrid-onsite position...
A creative Design Intern shares our commitment to design excellence, sustainability, and innovation as a part of our 2025 Summer Scholars... ...As part of this team, you will have the opportunity to shape architectural projects in a variety of typologies and scales for clients...
...Avenue, Verona, NJ. Full-time and part-time positions are available. Morning availability is required. Job Position: Cafe/Juice Bar Team Member (Full Time Position). 5 Star Juice & Coffee Bar looking for a Full-Time (Part-Time possible) team member to work with...